Research about basic technology of next generation supercomputers

INOGUCHI Laboratory
Professor：INOGUCHI Yasushi

E-mail：
［Research areas］
Massively Parallel Systems
［Keywords］
Massively parallel architecture, Parallel processing, Reconfigurable systems, Super computers, Domain Specific Architecture, CNN Chip

Skills and background we are looking for in prospective students

Programming skills such as C, Python, or HDL are desired. However, a student can learn programming after he/she enters our laboratory. Almost half students have programming skills when they entered to our laboratory, remained half students learn after they enter our laboratory.

What you can expect to learn in this laboratory

A student can learn several skills in the followings.

1. Design method of parallel computers. Basic knowledge to design next generation parallel systems such as Interconnections and routing.
2. How to use parallel systems. Parallel programming techniques such as MPI and OpenMP.
3. GPGPU computing. Programming skills to use CUDA or OpenAcc.
4. Design method of a digital circuit. How to design FPGAs and ASICs.
5. Designing skills to build a special purpose machine such as CNN.

【Job category of graduates】General electrical manufacturers, telecommunications companies, cloud ventures.

Research outline

Our laboratory researches about design method of massively parallel systems and parallel applications. Both hardware oriented research and software oriented research are our scope. The followings are our current research projects.
Recently, the DSA (Domain Specific Architecture) has been a hot topic to accelerate the execution speed of an application. Our laboratory develops suitable architectures for several applications such as CNN-oriented architecture.

1. Giga speed audio fingerprint detection and searching.
   Accelerate the detection speed of audio fingerprint using FPGAs and GPGPUs.
   Currently over than 1Gbps speed is established.
2. High-speed numerical solution of linear equation systems using GPGPUs.
   GPGPU has a great potential to solve a large-scale linear equation system in a short time, but memory capacity is one of the serious problems. We developed a new sparse matrix compression method for a GPGPU and reduce 35% memory usage.
3. Real time acoustic simulation using FPGAs or ASICs.

Our laboratory welcomes a student

• who wants to research next-generation computer systems that include CNN-oriented machines,
• who wants to use a massively parallel system or an FPGA,
• and who graduated from the department of chemistry or physics and is interested in computer systems.

A student can choose a research topic by both ways: decides his/her self or joins a research project in our laboratory.

Key publications

1. Faiz Al Faisal, M.M. Hafizur Rahman and Y. Inoguchi, "HFBN: An Energy Efficient High Performance Hierarchical Interconnection Network for Exa-scale Supercomputer", IEEE Access, Vol. 10, pp.3088-3104, Jan., 2022
2. T. Yiyu, Y. Inoguchi, M. Otani, Y. Iwaya and T. Tsuchiya, "A Real-Time Sound Field Rendering Processor", Applied Sciences, MDPI, Vol. 8, No. 1, 17 pages online, Jan., 2018
3. T. Kawamura, Y. Kazunori, T. Yamazaki, T. Iwamura, M. Watanabe and Y. Inoguchi, "A compression method for storage formats of sparse matrix in solving the large scale linear systems", Proc. In APDCM held in conjunction with 31rd IEEE IPDPS, pp.924-931, Orlando, FL, USA, Mar. 29, 2017

Equipment

Xilinx ALVEO U200s and Intel Arria10 GX FPGA systems, nVidia A100, V100, H100等 GPGPU Cluster,
Digital circuit design system, logic analyzers,
Massively parallel systems.