Yukinori Sato, Ph. D.

YukinoriSatoPic

2007 – 2015. Assistant Professor. Research Center for Advanced Computing Infrastructure, Japan Advanced Institute of Science and Technology.

B.S. from Tohoku University (2001), M.S. from Tohoku University(2003), Ph.D. from Tohoku University(2006)

Computer architecture, Computer system, supercomputing

Execution Profiling, Dynamic Compilation, Massive parallel processing,Reconfigurable processing

JST CREST: Development of System Software Technologies for post-Peta Scale High Performance Computing, “Software Technology that Deals with Deeper Memory Hierarchy in Post-petascale Era”, Oct. 2012 – Mar. 2017.

Committee

IEICE Technical Committee on Reconfigurable Systems (RECONF), Committee Member, 2015-.
IPSJ Special Interest Group on System Architecture, Committee, Apr. 2014 – Mar. 2016.
IPSJ Special Interest Group on HPC, Committee Member, 2007-2010.

Workshop Organizer

International Workshop on Software Engineering for Parallel Systems, SEPS (2015-2016: Workshop Co-Organizers). [link]

Program Chair

International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), with David Thomas (Imperial College) and Najjar Walid (UC Riverside) 2012.

Editing

IEICE Transactions on Electronics. Special Section on “Low-Power and High-Speed Chips” (July 2015 Issue), Guest Associate Editor
IPSJ Transactions on Advanced Computing Systems. Editorial Board Member. 2013- [link]

Conference Organizing Committee

Finance Chair, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2014. [link]
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), 2016: Registration Co-Chair, 2010-2015: Web manager. [link]
Web Chair, International Conference on Field-Programmable Technology (ICFPT), 2013. [link]
Vice Chair,The 2nd ARC/CPSY/RECONF High-Performance Computer System Design Contest, 2014. (Domestic) [link]
Local Arrangement, Summer United Workshops on Parallel, Distributed and Cooperative Processing, 2010. (Domestic) [link]
Organizer, HPC Workshop KANAZAWA 2013 (cosponsered by JAIST Research Center for Advanced Computing Infrastructure (RCACI), JAIST Research Center for Simulation Science (RSCC) and Cray Japan Inc.) (Domestic) [link]
Organizer, HPC Workshop KANAZAWA 2009 (cosponsored by JAIST and Cray Japan Inc.) (Domestic) [link]

Program Committee

IEEE International Conference on Parallel and Distributed Systems, ICPADS (2016, PC Member)
International Symposium on Computing and Networking, CANDAR (2015-2016, PC member)
International Conference for High Performance Computing, Networking, Storage, and Analysis, SC15 (Birds-of-a-Feather (BOF) Programming Languages Committee Member)
The International Conference on Field-Programmable Technology (ICFPT), 2014. [link]
International Symposium on Applied Reconfigurable Computing (ARC), 2012-2015. [link]
Annual Meeting on Advanced Computing System and Infrastructure (ACSI), 2015 [link]
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2013. [link]
IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips), 2008-2009. [link]
Workshop on Infrastructures for Software/Hardware co-design (WISH), 2010. [link]
IEICE International Workshop on Advances in Networking and Computing (WANC), 2013-2014. [link 1] [link 2]
Symposium on Advanced Computing Systems and Infrastructures (SACSIS), 2012-2013. (Domestic) [link]
First International Workshop on Software Technologies for Future Dependable Distributed Systems 2009.

Review

ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC) 2016, Second reviewer
IEEE International Conference on Parallel Processing (ICPP) 2015, Subreviewer
IEEE Transactions on Parallel and Distributed Systems, Reviewer. [link]
IEEE Transactions on Circuits and Systems for Video Technology, Reviewer. [link]
Elsevier Journal of Systems and Software, Reviewer
Elsevier Journal of Microprocessors and Microsystems, Reviewer
IEICE Transactions on Information and Systems, Reviewer. [link]
IEICE Transactions on Electronics, Reviewer. [link]
IEEE Micro, Reviewer, COOL Chips Special Issue, 2009. [link]
Interdisciplinary Information Sciences (Journal), 2009. Reviewer. [link]
IEEE International Conference on Application-specific Systems, Architectures and Processors, Secondary Reviewer. 2010, 2013.[link]
IEEE Circuit and Systems Society，7th Int’l Symp. on Communications and Information Technologies 2007, Reviewer.
IPSJ Symposium on High Performance Computing and Computational Science 2010, Reviewer.

Grants

JST CREST, co-PI, “Software Technology that Deals with Deeper Memory Hierarchy in Post-petascale Era”, Research and development of dynamic compilation technology for deeply hierarchal memory; September 2012 to March 2015, (\31,450,000) [link]
JSPS Grants-in-Aid for Scientific Research (KAKENHI), Challenging Exploratory Research, PI, “Data-driven custom pipeline accelerator system for big data processing.” April 2014 to March 2016, (\2,800,000) [link]
JSPS KAKENHI Grant-in-Aid for Young Scientists (B), PI, “Productive parallel instruction processing system using real-time dependency analysis.” April 2009 to March 2011. (\3,200,000) [link]
Grant for Joint Research about Cloud Computing Infrastructure from Creationline Inc. PI. 2012. (\500,000)
Grant for Joint Research about custom computing using FPGAs from Hitachi Information & Telecommunication Engineering, Ltd. Co-PI. 2007. (\500,000)